IMAPS -
Fall-2006 Packaging Symposium
on
Advanced Packaging for Optical & Electronics Components
(photo:
Thursday, October 26, 2006
IBM TJ
Emergency
Contact Phone: (914) 784-3600
IMAPS Technical Program – October 26, 2006
Watson
Research - Room 26-014
1:00
– Introduction to IMAPS Technical Program
David
Seeger
Manager, Electronic
& Optical Packaging, IBM Research,
Session
1 – Challenges in Ceramic to Organic Transition
Session chair: Benson
Chan, Endicott Interconnect Technologies, Inc., NY
1:05
– Challenges of Packaging When We Move from Ceramic to Organic
S.
B. Park and Soonwan Chung
Professors, Mechanical
Engineering, SUNY
1:30
–Underfill Interaction with a Pb-Free CSP Assembly Process and Reliability
Paul
Morganelli, PhD, Vinod
Mohan, Brian Wheelock, Antonio Prats and Tim Adams
Emerson & Cuming,
1:55
– Organic Substrates: Model for flip-chip analysis
Lorenzo
Valdevit et al.
Post Doctoral Scholar,
2:20
– Electromigration in Flip Chip Joints on
Organic Substrates
Jae-Woong
Nah and King-Ning Tu
Department of Materials
Science and Engineering, UCLA,
2:45
- 3:45 – Break (1 hour)
Session
2 – Materials, Components & Processes
Session chair: Frank Pompeo, IBM Systems & Technology Group, East
3:45
– Nanocomposites for Microelectronic Packaging
Applications
Emmanuel
P. Giannelis (Presented by Robert Rodriguez)
4:10
– Study of the Undercooling of Pb-free Solder Bumps…
Sung
K. Kang, M. G. Cho, P. Lauro, and Da-Yuan
Shih
IBM Research,
4:35
– A new backplane connector technology
Steve
Minich
Staff Product
Development Engineer, FCI,
5:00
– 3D
Package Miniaturization
David
Tuckerman
CTO, Tessera,
Tour: BlueGene Computer Facility,
Materials Research Laboratory
5:30 – 7:00: Social Hour / Dinner
Challenges of Packaging When We Move from
Ceramic to Organic
S. B. Park and Soonwan Chung
Professors, Mechanical Engineering, SUNY
sbpark@binghamton.edu
(607)
777-3415
ABSTRACT
Due
to manufacturing cost, the organic packages have been replacing the ceramic
packages in many
electronic
packaging applications. However, some concerns about reliability can be raised
since organic
materials
have unique characteristics compared to ceramics. Organics have larger
coefficient of thermal
expansion
compared to ceramics and can absorb significant amount of moisture during and
after process.
In
this presentation, the challenges of migrating to organic package are discussed
in a view of reliability
concerns.
Also,
traditional reliability assessment schemes are revisited. Conventionally,
reliability assessment of
solder
interconnects is conducted by ATC (Accelerated Thermal Cycling) that assumes
uniform
temperature
throughout the assembly because ATC is believed to be more damaging thermal
loading
condition
compared to PC (Power Cycling), which is similar to the actual field condition.
However, this is
not
always true in the case of organic packages because larger temperature gradient
between substrate and
PCB
and CTE combinations generate larger strain during PC rather than ATC.
Consequently, PC can be
severer
condition than ATC in the case of organic packages depending on the geometry
and CTE of chip,
substrate,
and PCB. In this talk, the reliability of board level interconnects for ceramic
and organic flip
chip
BGA (Ball Grid Array) packages is examined by comparing in between PC and ATC
conditions.
BIO
Dr.
Park received his Ph.D. at
began
his professional career at IBM Microelectronics Division as a
development
engineer in
in
the reliability engineering responsible for the reliability of IBM’s
corporate
flip chip technology in both leaded and lead-free solders
and
high performance packaging. After 7 years at IBM
Microelectronics
Division, Dr. SB Park started his academic career
at
publications
and holds 4 US patents. Dr. Park served for several
technical
committees including member of JEDEC 14-1 Reliability
Committee,
co-chair of iNEMI Modeling and Simulation TWG, and
chair of “Electronics Packaging”
council
in Soc. of Exp. Mechanics. He was a co-organizer of Co-Organizer of the 1st International
Symposium on Optical Methodologies and Metrologies for
Microelectronics and Photonics and
“Emerging technology” track in ITHERM 06.
Dr. Park research interest is physical reliability or
microelectronics
and MEMS packaging. His current projects include Pb-free
solder reliability, Material
and
packaging integrity of MEMS and Wafer Level packages, Experimental and
numerical analysis of
flexible
electronics, and development of Optomechanics for
small scale systems.
Underfill Interaction with a Pb-Free
CSP Assembly Process and Reliability
Paul Morganelli, PhD, Vinod
Mohan, *Brian Wheelock, Antonio Prats, Tim Adams
Emerson
& Cuming,
brian.wheelock@nstarch.com
(987)-436-9836
ABSTRACT
In
this study, we examined the interactions of three types of underfill
materials with a Pb-
Free
solder paste. Underfill formulations cured by
anhydride, base, and acid were assessed
for
changes in reactivity in the presence of Pb-free
solder paste residue. An analysis of
commercial
Pb-free solder paste was conducted, and the effect on
underfill reactivity of the
primary
components was explored. Reliability tests were conducted. Although some types
of
underfill chemistry are affected more than others by
solder paste residues, it was found
that
good reliability can still be obtained. It also was found that the underfill flux interaction
can
be managed by formulation.
BIO
Brian
Wheelock is a Senior Chemist with Emerson & Cuming. He
has
ten years experience in the development of underfills
for board
level
assembly and has co-authored several patents and
publications
in the areas of Pre-applied, NoFlow, and Capillary
UF
technology.
Organic substrates: a model for flip-chip
analysis
L. Valdevit, V. Khanna,
A. Sharma, S. Sri-Jayantha
IBM,
lorenzo@engineering.ucsb.edu
(857)
998-0578
D. Questad, K. Sikka
IBM
Systems and Technology
To
be submitted to Journal of
Microelectronics Reliability
ABSTRACT
We
present a mechanical characterization of organic substrates that accounts for
heterogeneity
both in the in-plane and out-of-plane directions. Systematic observation of the
board
files of a number of substrates of interest reveals primarily three recurrent
topological
arrangements
of copper and polymer; for each arrangement, the in-plane effective thermoelastic
properties
are calculated via appropriate composite materials models. The averaging
process
in the out-of-plane direction (i.e. the stacking effect) is modeled using standard
laminated
plate theory. The model is successfully applied to various regions of three
organic
substrates
of interest (mainly differing for the core thickness): the analytically
calculated
effective
Young’s moduli (E) and Coefficients of Thermal
Expansion (CTE) are shown to be
typically
within 10% of the experimental measurements. An important attribute of this
model
is its ability to provide substrate description at various levels of
complexity: a few
effective
properties are outputted that can be useful for further purely analytical
investigations;
at the same time, the model provides the full stiffness matrix for each region
of
the substrate, to be used for more detailed finite elements simulations of
higher-level
structures
(e.g. silicon die/underfill/substrate/cooling
solution assemblies). Preliminary
application
of this model to the warp analysis of three substrates of interest is presented
in the
end.
BIO
Lorenzo
Valdevit is currently a postdoctoral scholar at the
University of
Engineering
from the
Mechanical
and Aerospace Engineering from Princeton University. In
2005,
Dr. Valdevit worked at
where
he collaborated to the characterization of organic packages.
Current
research interests include thermo-mechanical analysis, design
and
optimization of multifunctional structures, primarily for aerospace
applications,
micro-fabrication of high-authority actuators as well as the
bio-chemo-mechanics
of mammalian cells.
Electromigration in flip chip joints on organic substrates
Jae-Woong Nah* and King-Ning Tu
Department
of Materials Science and Engineering, UCLA,
jnah@us.ibm.com
ABSTRACT
Flip chip technology has been widely applied for various
applications such as
telecommunications, computers, appliances, and so on. In a flip
chip technology, the need for
high-density interconnects in a cost effective flip chip package
was the motivation for using
organic substrates. For high-end devices on organic substrates,
the flip chip joints were made by
combination of the high melting 97Pb-3Sn on the chip side and
37Pb-63Sn on the organic
substrate side. The major advantage of using such a composite
solder joint is that the lowtemperature
joining of the two solders is comparable with the organic
substrate. However, during
electromigration, in addition to the compositional change by the moving of Pb atoms in the same
direction as the electrons, current crowding was observed inside
the UBM and it enhanced the
phase transformation of Cu to Cu3Sn and to Cu6Sn5 at the UBM/solder interface.
Due to the
growth of Cu6Sn5, the Cu UBM was consumed
rapidly, resulting in void formation induced
failure at the cathode side. The sequence of Cu UBM consumption
and void formation in
composite solder joints will be presented. To explore a strong
resistance against current
crowding induced electromigration
failure in flip chip joints, a very thick Cu pillar bump
combined with a shallow solder interconnect at 100 µm pitch for flip chip
applications on organic
substrates have been studied. The reduction of current crowding in
the solder region by using
thick Cu pillar bumps increased the reliability against electromigration induced failure. The
current distribution in a flip chip joint of a Cu pillar bump
combined with a shallow solder has
been confirmed by simulation. However, Kirkendall
void formation was found to be very serious
and enhanced by electromigration at the
Cu/Cu3Sn interface due
to the large Cu/Sn ratio. Since
this is a system of a limited amount of Sn
and an infinite supply of Cu, the Cu6Sn5 transforms to
the Cu3Sn
after all the Sn content in the solder bump is
consumed and the Cu3Sn
can grow very
thick, the vacancy flux that opposes the Cu flux will condense to
form Kirkendall voids. The
mechanism of electromigration induced Kirkendall void formation in the Cu pillar with the
shallow solder joint will be discussed.
BIO
Dr. Jae-Woong Nah received his Ph.D.
degree in materials
science and engineering from Korea Advanced Institute of
Science and Technology (KAIST) in 2004. Following receipt of
the Ph.D. degree, he joined the
Angeles, as a post doctoral research associate in Professor King-
Ning Tu’s group where he has worked on
development of new
flip chip structure and electromigration
in flip chip joints. Since
joining the IBM T. J. Watson research center as a post-doc in
September 2006, he has been involved in research and
development on materials and process for flip chip technology.
He has authored or co-authored more than 35 journal papers and
conference proceeding papers and hold a
Member of IEEE, IEEE-CPMT, TMS, and IMAPS.
Nanocomposites and Nanoparticle
Fluids for
Microelectronic Packaging Applications
Emmanuel P. Giannelis
Materials
Science and Engineering
epg2@cornell.edu
Presented by: Robert Rodriguez
Graduate
Student, Department of Physics
607-255-0463
rr256@cornell.edu
ABSTRACT
In
the first part of this talk, I will review our research effort in nanocomposites and
emphasize
work related to understanding their mechanical performance including our
latest
work with hierarchical nanocomposites via directed
assembly of nanoparticles. In
the
second part, I will present our recent work in “solvent-free” nanoparticle fluids.
These
new material systems based on inorganic nanoparticle
cores and a surface corona,
combine
fluidity and transport properties similar to molecular liquids with zero vapor
pressure.
By properly selecting the type, shape, or size of the core nanoparticles
and the
corona
chemistry, one could efficiently optimize any set of properties including
viscosity,
transparency,
refractive index, conductivity and surface tension.
BIO
Robert Rodriguez
Before
joining the PhD program at
received
his Bachelor of Science degree in Physics from the
year
graduate student and is expected to graduate in September
2008.
His research project is on characterizing and understanding
the
basic physics of solvent-free nanofluids, which are
new
materials
developed at
is
Emmanuel P. Giannelis in the Department of Materials
Science
&
Engineering.
Study of the Undercooling
of Pb-free, Flip-Chip Solder Bumps and In-situ
Observation of Solidification Process
Sung K. Kang, M. G. Cho, P. Lauro, and Da-Yuan Shih
kang@us.ibm.com
ABSTRACT
The
undercooling of flip-chip Pb-free
solder bumps was investigated by differential scanning
calorimetry (DSC) to understand the
effects of solder composition and volume, with and without
the
presence of an Under Bump Metallurgy (UBM). A large amount of the undercooling (as
large
as 90°C) was observed
with Sn-rich, flip-chip size solder bumps sitting in
a glass mold,
while
the corresponding undercooling was significantly
reduced in the presence of a wettable
UBM
surface. In addition, the solidification of an array of individual solder bumps
was
monitored
in-situ by video imaging technique during both heating up and cooling down
cycles.
Data
obtained by the optical imaging method is used to complement the DSC thermal
measurements.
A random solidification of the array of bumps was demonstrated during cooling
which
also spans a wide temperature range of 40-80°C. In contrast, an almost simultaneous
melting
of the bumps was observed during heating.
BIO
Sung K. Kang is a Research Staff Member in
the Electronic and
Optical
Packaging Department at the Thomas J. Watson Research
Center.
He received a B.S. degree in metallurgical engineering from
Science
and Metallurgy from the University of Pennsylvania. He was a
post-doctoral
research fellow at
Scientist
at
Assistant
Professor at Stevens Institute of Technology, and Senior
Scientist
at the International Nickel Company. In 1984, he joined IBM
at
the
microelectronic
interconnection technologies and materials, and
recently
on conducting adhesives and Pb-free soldering
technologies. He is an author or coauthor
of
35
of
Electronic Packaging & Interconnection Materials Committee of TMS (the
Minerals, Metals
&
Materials Society).
A New Backplane Connector Technology
Steve Minich
Staff
Product Development Engineer, FCI,
Steve.Minich@fciconnect.com
717-938-7384
ABSTRACT
Although
the predominant PCB attachment method for backplane connectors today is
press-fit
termination, future data rates will demand different connector technologies.
One
of
these alternate connector configurations will be surface
Even
with today's speeds there are many instances where system packaging constraints
exist
that would favor the use of surface mount connectors over press-fit. FCI has
performed
component and system level mechanical studies on AirMax
VS(r) backplane
connectors
with BGA terminations. The resulting data supports use of BGA connectors
for
such applications. Furthermore, a link simulation shows favorable high speed
performance
for a BGA connector footprint compared to a press-fit layout. FCI will be
commercializing
AirMax VS(r) BGA backplane connectors in early 2007.
BIO
Steven
E. Minich's current responsibilities include the
conceptualization
and development of high-speed backpanel
connectors.
He also engages in customer support activities
working
very closely with Marketing and Field Sales. Prior to
coming
to FCI in 1999, he worked at AMP Incorporated (now
Tyco
Electronics) for 6 years as a development engineer
spending
most of that time in the Signal Conditioning Products
Division
where he designed filtered electrical connectors. He
was
also selected as one of six participants worldwide to
participate
in AMP's full time Advanced Engineering
Development
Program in 1998. He has thirteen issued patents
in
electrical connector design. He graduated from
University
with a B.S. in Mechanical Engineering and is a licensed Professional Engineer
in
3D Package Miniaturization
David Tuckerman
CTO,
Tessera,
DTuckerman@tessera.com
ABSTRACT
This
presentation will provide an overview of selected electronic and optical
packaging
technologies
that make more efficient use of the 3rd (i.e., out of plane) dimension and
their
increasingly important role in enabling further miniaturization of portable
electronics.
Some specific examples having near-term commercial potential will be
described.
For example, a new ultralow profile fine-pitch 'Micro
Contact' chip-scale
packaging
technology is described that is well suited to chip stacking. A low-profile
high-yielding
image sensor chip packaging technology is also described, and the
prospects
for incorporating wafer-level optics to produce highly miniaturized camera
modules
is discussed. The presentation concludes with an overview of future trends and
challenges
associated with increased exploitation of the three-dimensional packaging and
interconnect
techniques.
BIO
Biography:
David B. Tuckerman is Senior Vice President and
Chief
Technical Officer at Tessera, Inc. in San Jose,
California.
Prior
to joining Tessera in 2003, he worked for 5 years as
a
venture
capitalist with CMEA Ventures in
to
that, he spent 7 years as co-founder and Chief Technical
Officer
of nCHIP Inc. (acquired by Flextronics in 1994),
where
he
developed advanced multichip module packaging
technologies.
Prior to founding nCHIP, he managed advanced
R&D
projects at Lawrence Livermore National Laboratory.
Prior
to LLNL, he made technical contributions to Josephson
junction
technology as an MIT co-op student at the IBM T. J.
PhD
in Electrical Engineering from
Graduate
publications,
and was honored as an IEEE Fellow "for contributions to high-performance
electronic
packaging and interconnection technologies, including the development of the
microchannel heat sink."